module OH_RXOHCAP_RAM128K_64_64(
   input                      CLKA,
   input                      WEA,
   input[10:0]                ADDRA,
   input[63:0]                DINA,
   input                      CLKB,
   input[10:0]                ADDRB,
   output[63:0]               DOUTB
   );

SDH_XLNX_RAM128K_64_64             INST_RAM128K_64_64(
   .clka                           (CLKA),
   .wea                            (WEA),
   .addra                          (ADDRA[10:0]),
   .dina                           (DINA[63:0]),
   .clkb                           (CLKB),
   .addrb                          (ADDRB[10:0]),
   .doutb                          (DOUTB[63:0])
   );

endmodule
